Design-Reuse

A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications

A novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models, particularly focusing on structured sparsity. Structured sparsity involves a ...
Forbes

SiFive Is Leading The Way For Innovation On RISC-V

The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...
Design-Reuse

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized ...
Semiconductor Engineering

Towards Base-Station-On-Chip: Wireless Communication Kernels On A RISC-V Vector Processor (TU Dresden, CeTI)

A new technical paper titled “Towards a Base-Station-on-Chip: RISC-V Hardware Acceleration for wireless communication” was published by researchers at TU Dresden and Centre for Tactile Internet with ...