EDN

Clock multiplier offers 5-ps period jitter

Available in a TSSOP-16 package, the NB3N3020 programmable clock multiplier can generate up to 26 different clock frequencies from a single-input source on its LVPECL/ LVCMOS output. The device has a ...
EDN

Clock oscillators offer low cycle-to cycle jitter

The SiT9001 and SiT9002 spread-spectrum clock oscillators provide a cycle-to-cycle jitter of less than 30 ps and include an embedded MEMS resonator as the clock reference, which eliminates the need ...
Electronic Design

Clock Trims Cycle-To-Cycle and Period Jitter

Promising precise clock generation in networking and other applications, the CY22180 clock achieves a period and cycle-to-cycle jitter output of less than 75 ps over its entire output-frequency range, ...
Seeking Alpha

Skyworks Sets New Benchmark in Ultra-Low Jitter Clock Buffers for High-Speed Connectivity

New SKY53510/80/40 Family of Clock Fanout Buffers are Purpose-Built for Data Centers, Wireless Networks, and PCIe Gen 7 Applications IRVINE, Calif.--(BUSINESS WIRE)-- Skyworks Solutions, Inc. (SWKS), ...
Business Wire

IDT Introduces Ultra-Low-Jitter Family of LVCMOS Clock Buffers

SAN JOSE, Calif.--(BUSINESS WIRE)--Integrated Device Technology, Inc. (IDT®) (NASDAQ:IDTI) introduced today a new family of clock buffers that deliver best-in-class jitter performance in a compact ...
Electronic Design

How Best to Measure SSC on Data

Spread spectrum clocking (SSC) is used in many computer interfaces such as PCI Express and Serial ATA to improve the EMI performance of the interface. It takes the form of frequency modulation (FM) of ...