A new technical paper titled “A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations” was published by ...
CHANDLER, Ariz., Aug. 5, 2019 /PRNewswire/ -- As the computational demands of artificial intelligence (AI) and machine learning workloads accelerate, traditional parallel attached DRAM memory has ...
CAMBRIDGE, UK – Oct. 7, 2008 – ARM [(LSE: ARM); (Nasdaq: ARMH)] today announced the ARM PrimeCell low-power DDR2 (LPDDR2) dynamic memory controller (PL342), which provides a high-performance interface ...
U.S. lawmakers called for memory to be added to chip controls, days after a bill was passed to further limit Chinese access ...
A technical paper titled “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator” was published by researchers at ETH Zurich. “We present Ramulator 2.0, a highly modular and extensible DRAM ...
Perhaps the biggest task that processor and system designers have to wrestle with these days is how to keep heavily cored and massively threaded processors fed with data. Modern CPUs have anywhere ...
The number of systems-on-a-chip (SoCs) that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to double-data-rate (DDR) SDRAM interfaces such as ...
In 2015, researchers reported a surprising discovery that stoked industry-wide security concerns—an attack called RowHammer that could corrupt, modify, or steal sensitive data when a simple user-level ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results